The present invention relates to an embedded package and a method for manufacturing the same.
As a space in which a semiconductor package is to be mounted gradually decreases with the trend of portable electronic appliances toward miniaturization and high capacity, research for increasing mounting efficiency is being continuously conducted. In order to increase mounting efficiency, a semiconductor package is may be made light, slim, compact and miniature. In an attempt therefor, an embedded package, in which chips are disposed not on the surface of a substrate but in the substrate, has been suggested in the art.
In order to realize high capacity and miniaturization of an embedded package, the number of chips which are embedded in a substrate may increase over 2, and the chips may be vertically arranged. However, if the number of chips which are vertically arranged increases, the number of layers of circuit patterns for electrically connecting the chips with an outside increases in proportion to the number of chips, which may lead to an increase in the thickness of the embedded package. Consequently, a problem is caused in that the embedded package becomes thick.